0 to 9999 bcd counter on seven segment(VHDL code) Synthesizeble

--Note: while building Project do include sec_clk and seg7 files which i posted

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity c09 is
port( rst,clk: in std_logic;
      op0,op1,op2,op3: out std_logic_vector(6 downto 0));
end c09;

architecture count of c09 is

component sec_clk
Port (
           clk             : in  std_logic;
           rst : in std_logic;
           op  : out std_logic
           );
    end component;
   
component seg7
port(m: in integer range 0 to 15;
     num: out std_logic_vector(6 downto 0));
end component;


signal flag: std_logic;
signal a: integer range 0 to 10;
signal b: integer range 0 to 10;
signal c: integer range 0 to 10;
signal d: integer range 0 to 10;
begin

c1: sec_clk port map(clk,rst,flag);

process(rst,flag)
variable m0: integer range 0 to 10:=0;
variable m1: integer range 0 to 10:=0;
variable m2: integer range 0 to 10:=0;
variable m3: integer range 0 to 10:=0;

begin

if rst='0' then
m0:=0;
m1:=0;
m2:=0;
m3:=0;
elsif flag'event and flag='1' then
a<=m0;
b<=m1;
c<=m2;
d<=m3;
if m0 /= 9 then
m0:= m0 + 1;
elsif m0=9 and m1 /= 9 then
m0:=0;
m1:= m1 + 1;
elsif m1=9 and m2 /= 9 and m0=9 then
m1:=0;
m0:=0;
m2:= m2 + 1;
elsif m2=9 and m3/= 9 and m0=9 and m1=9 then
m1:=0;
m0:=0;
m2 :=0;
m3 := m3 + 1;
elsif m3=9 then
m0:=0;
m1:=0;
m2:=0;
m3:=0;
end if;
end if;

end process;

z0: seg7 port map(a,op0);
z1: seg7 port map(b,op1);
z2: seg7 port map(c,op2);
z3: seg7 port map(d,op3);

end count;



 here is my youtube video of above project: http://www.youtube.com/watch?v=RrPzS5FLz3k

bcd to seven seg decoder (modified using integer data type) in vhdl(synthesizable)

This code is generally used as component:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity seg7 is

port(m: in integer range 0 to 15; -- m is decleared as INTEGER
     num: out std_logic_vector(6 downto 0));
end seg7;

architecture s7 of seg7 is
begin
process(m)
begin
case m is
when 0 => num<="1000000";
when 1 => num<="1111001";
when 2 => num<="0100100";
when 3 => num<="0110000";
when 4 => num<="0011001";
when 5 => num<="0010010";
when 6 => num<="0000010";
when 7 => num<="1111000";
when 8 => num<="0000000";
when 9 => num<="0010000";
when 10 => num<="0001000";  -- hex(a)
when 11 => num<="0000011";  -- hex(b)
when 12 => num<="1000110";  -- hex(c)
when 13 => num<="0100001";  -- hex(d)
when 14 => num<="0000110";  -- hex(e)
when 15 => num<="0001110";  -- hex(f)
when others=> num<="1111111";
end case;
end process;
end s7;

bcd to seven seg decoder in vhdl(synthesizable)

library ieee;
use ieee.std_logic_1164.all;

entity seg7 is

port(m: in std_logic_vector(3 downto 0);
     num: out std_logic_vector(6 downto 0));
end seg7;

architecture sseg of seg7 is
begin
process(m)
begin
if(m="0000") then
num<="1000000";
elsif(m="0001") then
num<="1111001";
elsif(m="0010") then
num<="0100100";
elsif(m="0011") then
num<="0110000";
elsif(m="0100") then
num<="0011001";
elsif(m="0101") then
num<="0010010";
elsif(m="0110") then
num<="0000010";
elsif(m="0111") then
num<="1111000";
elsif(m="1000") then
num<="0000000";
elsif(m="1001") then
num<="0010000";
else
num<="1111111";
end if;
end process;
end sseg;

VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)

CODE:

library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.numeric_std.all;

 entity sec_clk is
    Port (
           Clk             : in  std_logic;
           rst: in std_logic;
           op       : out std_logic
    );
 end sec_clk;

 architecture RTC of sec_clk is
   constant max_count : natural := 24000000;
-- I used 24MHz clock
  
 begin
      
    compteur : process(Clk,rst)
        variable count : natural range 0 to max_count;
    begin
        if rst = '0' then
            count := 0;
            op <= '1';
        elsif rising_edge(Clk) then
            if count < max_count/2 then
                op    <='1';
                count := count + 1;
            elsif count < max_count then
                op    <='0';
                count := count + 1;
            else
                count := 0;
                op    <='1';
            end if;
        end if;
    end process compteur;
 end RTC;

NOTE: THE BLOG AUTHOR VIPIN "Clock Frequency converter in VHDL" HAVE COPIED THE ABOVE CODE FOR CLOCK DIVIDER FROM MY BLOG AND WHEN CONTACTED HE STATES THAT ITS HIS OWN CODE. PLEASE TAKE NOTE.