Initializing M4K blocks for RAM. (For Altera FPGA users)

Hello Everybody.

It seems you are having problem about how to initialize on-board memory using Megafunction Library and M4K blocks. (I am using Quartus II 10.1 SP1, but procees will be similar all other versions)

So here are the steps of the solution:

Start Quartus II and open new project.

 

 Open the MegaFunction Wizard

Select the 'Create New megaFunction' Option

Select the Memory Compiler from list

Select RAM 1 Port and give name to output file

After clicking Next, select the no. of bits per block (In this case its 4 bits)

Select no. of words or blocks of 4-bits you want (In this case 32 blocks, I use 'blocks' though 'words' is proper term)

Select the memory block type as M4K (It doesnt matter if you keep that Auto)

Click Next. Dont change anything on this page

Now select the second option if you want to enter data in memory before programming

To create hex file keep the MegaFunction window as it is and click on the File>New>Intel-hex File in Quartus II window

Then make the proper changes in words and wordsize field

Add whatever data you want in the respective blocks (It will only take a 4 bit no. as we have set the word size as 4)

Save the file be any relevant name you want and then open the MegaFunction window and select the file

Click Next till you get the this window and select the Instantiation file option

Click finish and then open the Instantiation and Component file from File>Open>(Your destination of project)>*_inst.vhd and *.cmp

Then add the Code as follows and make necessary changes to the Port Map field as per your project specifications

If you want to, then you can follow the process rather can use the process with my SRAM interface example project. It will make you more perfect. You can check necessary changes required for my project in .vhd file I attached. Mail me your querries or suggestions on prasadp4009@gmail.com

Enjoy programming...!!

Interfacing (RAM) Onboard M4K memory blocks of Cyclone II Altera De1 board

This code shows how to store or interface the SRAM with any of your code. You can integrate this code in your projects for storing data. I will upload the interface of RAM with RTC code I designed for storing Date.

In this code I used the on-board M4K memory blocks on Altera DE1 board as RAM in 32 words i.e. 32 address locations of 4-bit. The RAM is initialized through Altera's MegaFunction IP Library. Comment if you don't know how to initialize RAM on any Altera board. I stored some variables like 2,4,6,8 on some starting locations to check if its working. I also added feature of manual address incrementation and data i/p.

For manual data entry you have to use four switches on Altera De1 board viz.

• SW0 --LSB
• SW1
• SW2
• SW3 --MSB

To write data press KEY3 and to increment address location press KEY0.

Read operation will be done Automatically, as I have interfaced the BCD to 7SEG (modified seg7.vhd in my previous posts) decoder directly to data out of RAM. You will get to see the stored digit on 7Seg display no.1.

You can directly interface the write enable, I/P and O/P of data and address in your code with only some minor changes.

If you have any qurries feel free to Comment directly on post instead of mailing me so other people will also get some help from it. You still can mail me your querries and Ideas at prasadp4009@gmail.com.

Download liks:

• Main Entity sram_test.vhd     : sram_test.vhd
• Altera DE1 Quartus .sof file  : sram.sof
• Megafunction file                  : srm.vhd
• Seg7 modified                      : seg7.vhd

Video:

RTC on FPGA with manual set synthesizeble VHDL code.

Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great.

(Input freq 24MHz., top-level entity DigiClock)

Video will be uploaded soon.

On DE1 board: Push button functions.

• Key0: Reset
• Key1: Hour set (Key3 kept pressed)
• Key2: Minute set (Key3 kept pressed)
• Key3: Set enable.

Download links:

• DigiClock.sof   --DE1 board .sof file
• DigiClock.vhd
• manu_clk.vhd
• sec_clk.vhd
• min_clk.vhd
• seg7.vhd
• DigicClock.pof --DE1 board only (ActiveSerial Prog. file with EPCS4 device selected)

Video : 

Do test the codes. If you have any querries do comment or mail me at prasadp4009@gmail.com.

Enjoy Programming..!!

Display on VGA Monitor by FPGA(VHDL code Synthesizable, 640X480 resol, 60Hz)

This code is for displaying a simple ball bouncing on your monitor screen. As the monitor requires 60 Hz refresh rate i.e. to replace each pixel 60 times, it requires approx 40 ns. So to synchronize it with the FPGA processing speed, I used PLL with 50 MHz i/p clock dividing it to 25 MHz which scans each pixel in 40 ns.

The Video Synchronization file I created is VGAS which has 5 o/ps viz.

• red_out
• green_out
• blue_out
• horiz_sync_out
• vert_sync_out

These are connected to the VGA controller which must have be present on your FPGA board (present on all DE series board of Altera, I dont know about Xilinx). For the pins check the your board manual.

The VGAS.vhd file can be used as common file for all your FPGA projects(for dividing 50Hz clock as I have used PLL which is already present on DE1 board. So if you have DE1 board its well and good you can directly use the code with the syncclk.vhd included. If dont just a minor modification in i/p clock signal with 25MHz in VGAS.vhd and removing syncclk.vhd and its component in VGAS.vhd will work.)

The Ballm.vhd is used to create display on Monitor. For DE1 users you can diretly program the SOF file i hav provided in download links.

Post your replies and comments. For the projects or querries you have you can mail me on prasadp4009@gmail.com .

Be the follower, if you like my posts.

Enjoy programming.

Video link: http://www.youtube.com/watch?v=QcCdkWG-rmM

Download links for files:


http://www.4shared.com/file/_7V3nyj9/Ballm.html
http://www.4shared.com/file/8pE2Yhz2/Ballm.html
http://www.4shared.com/file/mqnCQJs0/sycclk.html
http://www.4shared.com/file/JsUb67B4/VGAS.html

Synthesizable RTC in VHDL

The code given is only for clock digit incrementation. For components in clock like min_clk and sec_clk, refer my previous codes.

VHDL code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clk12 is
port(
      clk: in std_logic;
      rst: in std_logic;
      op: out std_logic;
      op0,op1,op2,op3: out std_logic_vector(6 downto 0)
      );
     
end clk12;

architecture clock of clk12 is


component sec_clk
Port (
           clk : in std_logic;
           op  : out std_logic
     );
    end component;

component min_clk
Port (
           clk : in std_logic;
           rst : in std_logic;
           op  : out std_logic
     );
    end component;
   
   
component seg7
port(m: in integer range 0 to 10;
     num: out std_logic_vector(6 downto 0));
end component;


signal flag: std_logic;
signal sflag: std_logic;

signal a: integer range 0 to 10;
signal b: integer range 0 to 6;
signal c: integer range 0 to 10;
signal d: integer range 0 to 3;


begin

c1: sec_clk port map(clk,sflag);
c2: min_clk port map(sflag,rst,flag);
op<=sflag;

process(flag,rst)

variable m0: integer range 0 to 10:=0;
variable m1: integer range 0 to 6:=0;
variable m2: integer range 0 to 10:=2;
variable m3: integer range 0 to 3:=1;

begin
     a<=m0;
     b<=m1;
     c<=m2;
     d<=m3;
     if rst='0' then
     m0:=0;
     m1:=0;
     m2:=2;
     m3:=1;    
     elsif rising_edge(flag) then
     if  m0/=9 then
         m0:= m0+1;
        elsif  m0=9 and  m1/=5  then
         m0:=0;
         m1:= m1+1;
        elsif  m0=9 and  m1=5 and  m2/=9 and  m3=0 then
         m0:=0;
         m1:=0;
         m2:= m2+1;
        elsif  m0=9 and  m1=5 and  m2=9 and  m3=0 then
         m0:=0;
         m1:=0;
         m2:=0;
         m3:=1;
        elsif  m3=1 and  m2/=2 and  m1=5 and  m0=9 then
         m2:= m2+1;
        elsif  m3=1 and  m2=2 and  m1=5 and  m0=9 then
         m0:=0;
         m1:=0;
         m2:=1;
         m3:=0;
        end if; 
        end if;   
   
    end process;
   
    z0: seg7 port map(a,op0);
    z1: seg7 port map(b,op1);
    z2: seg7 port map(c,op2);
    z3: seg7 port map(d,op3);

end clock;



Note: The clock cant be set manually. It starts from 12:00. I tried my best to add the manual set function but didnt succeed. But I assure that manual set will also be there in couple of time. Suggetions are most welcome.

Video link: http://www.youtube.com/watch?v=1dbTi2PMgcU

Quartus SOF file for DE1 board only: Digiclk(for DE1 board only).SOF

Check the new code with hr and min manual set: RTC with maual set

Enjoy Programming.

0 to 9999 bcd counter on seven segment(VHDL code) Synthesizeble

--Note: while building Project do include sec_clk and seg7 files which i posted

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity c09 is
port( rst,clk: in std_logic;
      op0,op1,op2,op3: out std_logic_vector(6 downto 0));
end c09;

architecture count of c09 is

component sec_clk
Port (
           clk             : in  std_logic;
           rst : in std_logic;
           op  : out std_logic
           );
    end component;
   
component seg7
port(m: in integer range 0 to 15;
     num: out std_logic_vector(6 downto 0));
end component;


signal flag: std_logic;
signal a: integer range 0 to 10;
signal b: integer range 0 to 10;
signal c: integer range 0 to 10;
signal d: integer range 0 to 10;
begin

c1: sec_clk port map(clk,rst,flag);

process(rst,flag)
variable m0: integer range 0 to 10:=0;
variable m1: integer range 0 to 10:=0;
variable m2: integer range 0 to 10:=0;
variable m3: integer range 0 to 10:=0;

begin

if rst='0' then
m0:=0;
m1:=0;
m2:=0;
m3:=0;
elsif flag'event and flag='1' then
a<=m0;
b<=m1;
c<=m2;
d<=m3;
if m0 /= 9 then
m0:= m0 + 1;
elsif m0=9 and m1 /= 9 then
m0:=0;
m1:= m1 + 1;
elsif m1=9 and m2 /= 9 and m0=9 then
m1:=0;
m0:=0;
m2:= m2 + 1;
elsif m2=9 and m3/= 9 and m0=9 and m1=9 then
m1:=0;
m0:=0;
m2 :=0;
m3 := m3 + 1;
elsif m3=9 then
m0:=0;
m1:=0;
m2:=0;
m3:=0;
end if;
end if;

end process;

z0: seg7 port map(a,op0);
z1: seg7 port map(b,op1);
z2: seg7 port map(c,op2);
z3: seg7 port map(d,op3);

end count;



 here is my youtube video of above project: http://www.youtube.com/watch?v=RrPzS5FLz3k

bcd to seven seg decoder (modified using integer data type) in vhdl(synthesizable)

This code is generally used as component:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity seg7 is

port(m: in integer range 0 to 15; -- m is decleared as INTEGER
     num: out std_logic_vector(6 downto 0));
end seg7;

architecture s7 of seg7 is
begin
process(m)
begin
case m is
when 0 => num<="1000000";
when 1 => num<="1111001";
when 2 => num<="0100100";
when 3 => num<="0110000";
when 4 => num<="0011001";
when 5 => num<="0010010";
when 6 => num<="0000010";
when 7 => num<="1111000";
when 8 => num<="0000000";
when 9 => num<="0010000";
when 10 => num<="0001000";  -- hex(a)
when 11 => num<="0000011";  -- hex(b)
when 12 => num<="1000110";  -- hex(c)
when 13 => num<="0100001";  -- hex(d)
when 14 => num<="0000110";  -- hex(e)
when 15 => num<="0001110";  -- hex(f)
when others=> num<="1111111";
end case;
end process;
end s7;

bcd to seven seg decoder in vhdl(synthesizable)

library ieee;
use ieee.std_logic_1164.all;

entity seg7 is

port(m: in std_logic_vector(3 downto 0);
     num: out std_logic_vector(6 downto 0));
end seg7;

architecture sseg of seg7 is
begin
process(m)
begin
if(m="0000") then
num<="1000000";
elsif(m="0001") then
num<="1111001";
elsif(m="0010") then
num<="0100100";
elsif(m="0011") then
num<="0110000";
elsif(m="0100") then
num<="0011001";
elsif(m="0101") then
num<="0010010";
elsif(m="0110") then
num<="0000010";
elsif(m="0111") then
num<="1111000";
elsif(m="1000") then
num<="0000000";
elsif(m="1001") then
num<="0010000";
else
num<="1111111";
end if;
end process;
end sseg;

VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)

CODE:

library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.numeric_std.all;

 entity sec_clk is
    Port (
           Clk             : in  std_logic;
           rst: in std_logic;
           op       : out std_logic
    );
 end sec_clk;

 architecture RTC of sec_clk is
   constant max_count : natural := 24000000;
-- I used 24MHz clock
  
 begin
      
    compteur : process(Clk,rst)
        variable count : natural range 0 to max_count;
    begin
        if rst = '0' then
            count := 0;
            op <= '1';
        elsif rising_edge(Clk) then
            if count < max_count/2 then
                op    <='1';
                count := count + 1;
            elsif count < max_count then
                op    <='0';
                count := count + 1;
            else
                count := 0;
                op    <='1';
            end if;
        end if;
    end process compteur;
 end RTC;

NOTE: THE BLOG AUTHOR VIPIN "Clock Frequency converter in VHDL" HAVE COPIED THE ABOVE CODE FOR CLOCK DIVIDER FROM MY BLOG AND WHEN CONTACTED HE STATES THAT ITS HIS OWN CODE. PLEASE TAKE NOTE.