RTC on FPGA with manual set synthesizeble VHDL code.

Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great.

(Input freq 24MHz., top-level entity DigiClock)

Video will be uploaded soon.

On DE1 board: Push button functions.

• Key0: Reset
• Key1: Hour set (Key3 kept pressed)
• Key2: Minute set (Key3 kept pressed)
• Key3: Set enable.

Download links:

• DigiClock.sof   --DE1 board .sof file
• DigiClock.vhd
• manu_clk.vhd
• sec_clk.vhd
• min_clk.vhd
• seg7.vhd
• DigicClock.pof --DE1 board only (ActiveSerial Prog. file with EPCS4 device selected)

Video : 

Do test the codes. If you have any querries do comment or mail me at prasadp4009@gmail.com.

Enjoy Programming..!!

Synthesizable RTC in VHDL

The code given is only for clock digit incrementation. For components in clock like min_clk and sec_clk, refer my previous codes.

VHDL code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clk12 is
port(
      clk: in std_logic;
      rst: in std_logic;
      op: out std_logic;
      op0,op1,op2,op3: out std_logic_vector(6 downto 0)
      );
     
end clk12;

architecture clock of clk12 is


component sec_clk
Port (
           clk : in std_logic;
           op  : out std_logic
     );
    end component;

component min_clk
Port (
           clk : in std_logic;
           rst : in std_logic;
           op  : out std_logic
     );
    end component;
   
   
component seg7
port(m: in integer range 0 to 10;
     num: out std_logic_vector(6 downto 0));
end component;


signal flag: std_logic;
signal sflag: std_logic;

signal a: integer range 0 to 10;
signal b: integer range 0 to 6;
signal c: integer range 0 to 10;
signal d: integer range 0 to 3;


begin

c1: sec_clk port map(clk,sflag);
c2: min_clk port map(sflag,rst,flag);
op<=sflag;

process(flag,rst)

variable m0: integer range 0 to 10:=0;
variable m1: integer range 0 to 6:=0;
variable m2: integer range 0 to 10:=2;
variable m3: integer range 0 to 3:=1;

begin
     a<=m0;
     b<=m1;
     c<=m2;
     d<=m3;
     if rst='0' then
     m0:=0;
     m1:=0;
     m2:=2;
     m3:=1;    
     elsif rising_edge(flag) then
     if  m0/=9 then
         m0:= m0+1;
        elsif  m0=9 and  m1/=5  then
         m0:=0;
         m1:= m1+1;
        elsif  m0=9 and  m1=5 and  m2/=9 and  m3=0 then
         m0:=0;
         m1:=0;
         m2:= m2+1;
        elsif  m0=9 and  m1=5 and  m2=9 and  m3=0 then
         m0:=0;
         m1:=0;
         m2:=0;
         m3:=1;
        elsif  m3=1 and  m2/=2 and  m1=5 and  m0=9 then
         m2:= m2+1;
        elsif  m3=1 and  m2=2 and  m1=5 and  m0=9 then
         m0:=0;
         m1:=0;
         m2:=1;
         m3:=0;
        end if; 
        end if;   
   
    end process;
   
    z0: seg7 port map(a,op0);
    z1: seg7 port map(b,op1);
    z2: seg7 port map(c,op2);
    z3: seg7 port map(d,op3);

end clock;



Note: The clock cant be set manually. It starts from 12:00. I tried my best to add the manual set function but didnt succeed. But I assure that manual set will also be there in couple of time. Suggetions are most welcome.

Video link: http://www.youtube.com/watch?v=1dbTi2PMgcU

Quartus SOF file for DE1 board only: Digiclk(for DE1 board only).SOF

Check the new code with hr and min manual set: RTC with maual set

Enjoy Programming.

0 to 9999 bcd counter on seven segment(VHDL code) Synthesizeble

--Note: while building Project do include sec_clk and seg7 files which i posted

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity c09 is
port( rst,clk: in std_logic;
      op0,op1,op2,op3: out std_logic_vector(6 downto 0));
end c09;

architecture count of c09 is

component sec_clk
Port (
           clk             : in  std_logic;
           rst : in std_logic;
           op  : out std_logic
           );
    end component;
   
component seg7
port(m: in integer range 0 to 15;
     num: out std_logic_vector(6 downto 0));
end component;


signal flag: std_logic;
signal a: integer range 0 to 10;
signal b: integer range 0 to 10;
signal c: integer range 0 to 10;
signal d: integer range 0 to 10;
begin

c1: sec_clk port map(clk,rst,flag);

process(rst,flag)
variable m0: integer range 0 to 10:=0;
variable m1: integer range 0 to 10:=0;
variable m2: integer range 0 to 10:=0;
variable m3: integer range 0 to 10:=0;

begin

if rst='0' then
m0:=0;
m1:=0;
m2:=0;
m3:=0;
elsif flag'event and flag='1' then
a<=m0;
b<=m1;
c<=m2;
d<=m3;
if m0 /= 9 then
m0:= m0 + 1;
elsif m0=9 and m1 /= 9 then
m0:=0;
m1:= m1 + 1;
elsif m1=9 and m2 /= 9 and m0=9 then
m1:=0;
m0:=0;
m2:= m2 + 1;
elsif m2=9 and m3/= 9 and m0=9 and m1=9 then
m1:=0;
m0:=0;
m2 :=0;
m3 := m3 + 1;
elsif m3=9 then
m0:=0;
m1:=0;
m2:=0;
m3:=0;
end if;
end if;

end process;

z0: seg7 port map(a,op0);
z1: seg7 port map(b,op1);
z2: seg7 port map(c,op2);
z3: seg7 port map(d,op3);

end count;



 here is my youtube video of above project: http://www.youtube.com/watch?v=RrPzS5FLz3k

bcd to seven seg decoder (modified using integer data type) in vhdl(synthesizable)

This code is generally used as component:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity seg7 is

port(m: in integer range 0 to 15; -- m is decleared as INTEGER
     num: out std_logic_vector(6 downto 0));
end seg7;

architecture s7 of seg7 is
begin
process(m)
begin
case m is
when 0 => num<="1000000";
when 1 => num<="1111001";
when 2 => num<="0100100";
when 3 => num<="0110000";
when 4 => num<="0011001";
when 5 => num<="0010010";
when 6 => num<="0000010";
when 7 => num<="1111000";
when 8 => num<="0000000";
when 9 => num<="0010000";
when 10 => num<="0001000";  -- hex(a)
when 11 => num<="0000011";  -- hex(b)
when 12 => num<="1000110";  -- hex(c)
when 13 => num<="0100001";  -- hex(d)
when 14 => num<="0000110";  -- hex(e)
when 15 => num<="0001110";  -- hex(f)
when others=> num<="1111111";
end case;
end process;
end s7;

bcd to seven seg decoder in vhdl(synthesizable)

library ieee;
use ieee.std_logic_1164.all;

entity seg7 is

port(m: in std_logic_vector(3 downto 0);
     num: out std_logic_vector(6 downto 0));
end seg7;

architecture sseg of seg7 is
begin
process(m)
begin
if(m="0000") then
num<="1000000";
elsif(m="0001") then
num<="1111001";
elsif(m="0010") then
num<="0100100";
elsif(m="0011") then
num<="0110000";
elsif(m="0100") then
num<="0011001";
elsif(m="0101") then
num<="0010010";
elsif(m="0110") then
num<="0000010";
elsif(m="0111") then
num<="1111000";
elsif(m="1000") then
num<="0000000";
elsif(m="1001") then
num<="0010000";
else
num<="1111111";
end if;
end process;
end sseg;