bcd to seven seg decoder in vhdl(synthesizable)

library ieee;
use ieee.std_logic_1164.all;

entity seg7 is

port(m: in std_logic_vector(3 downto 0);
     num: out std_logic_vector(6 downto 0));
end seg7;

architecture sseg of seg7 is
begin
process(m)
begin
if(m="0000") then
num<="1000000";
elsif(m="0001") then
num<="1111001";
elsif(m="0010") then
num<="0100100";
elsif(m="0011") then
num<="0110000";
elsif(m="0100") then
num<="0011001";
elsif(m="0101") then
num<="0010010";
elsif(m="0110") then
num<="0000010";
elsif(m="0111") then
num<="1111000";
elsif(m="1000") then
num<="0000000";
elsif(m="1001") then
num<="0010000";
else
num<="1111111";
end if;
end process;
end sseg;

VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)

CODE:

library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.numeric_std.all;

 entity sec_clk is
    Port (
           Clk             : in  std_logic;
           rst: in std_logic;
           op       : out std_logic
    );
 end sec_clk;

 architecture RTC of sec_clk is
   constant max_count : natural := 24000000;
-- I used 24MHz clock
  
 begin
      
    compteur : process(Clk,rst)
        variable count : natural range 0 to max_count;
    begin
        if rst = '0' then
            count := 0;
            op <= '1';
        elsif rising_edge(Clk) then
            if count < max_count/2 then
                op    <='1';
                count := count + 1;
            elsif count < max_count then
                op    <='0';
                count := count + 1;
            else
                count := 0;
                op    <='1';
            end if;
        end if;
    end process compteur;
 end RTC;

NOTE: THE BLOG AUTHOR VIPIN "Clock Frequency converter in VHDL" HAVE COPIED THE ABOVE CODE FOR CLOCK DIVIDER FROM MY BLOG AND WHEN CONTACTED HE STATES THAT ITS HIS OWN CODE. PLEASE TAKE NOTE.

Optimization techniques

To optimize the memory size of program(for microcontrollers)
 
    1. If you are working with 8 bit of data or no. between 0 to 255 then use char datatype.

    Example:
    int j = 0;
    for ( j =  0; j<=100 ; j++);

    Here instead of int use char. It will help u in optimizing program by a bunch of byte.
 
 
    2. Use just if rather than if-else or switch or array. It saves a lot of space.

    3. Design your own algorithm for any data (in which there are options to be selected) which can be obtainded by just subtracting or adding a no. or combination rather than using switch or if-else statements.

   4. Always try to design a nice logic, because you have brain.


more to come... till then enjoy programming..