RTC on FPGA with manual set synthesizeble VHDL code.

Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great.

(Input freq 24MHz., top-level entity DigiClock)

Video will be uploaded soon.

On DE1 board: Push button functions.

• Key0: Reset
• Key1: Hour set (Key3 kept pressed)
• Key2: Minute set (Key3 kept pressed)
• Key3: Set enable.

Download links:

• DigiClock.sof   --DE1 board .sof file
• DigiClock.vhd
• manu_clk.vhd
• sec_clk.vhd
• min_clk.vhd
• seg7.vhd
• DigicClock.pof --DE1 board only (ActiveSerial Prog. file with EPCS4 device selected)

Video : 

Do test the codes. If you have any querries do comment or mail me at prasadp4009@gmail.com.

Enjoy Programming..!!